Azernews.Az

by Alimat Aliyeva

Samsung Electronics announced on Wednesday that it has demonstrated what is described as the industry’s first vertically stacked transistor at a record-small scale, a breakthrough design aimed at packing significantly more computing power into the same chip area, AzerNEWS reports, citing Korean media.

The technology, known as a 3D Stacked FET (field-effect transistor), arranges transistors on top of each other rather than side by side—similar to replacing single-story houses with a multi-story apartment building. In theory, this approach could nearly double transistor density while also improving power efficiency.

The research was presented at the 2026 VLSI Symposium in Honolulu, Hawaii—one of the semiconductor industry’s most important academic conferences. According to reports, the work attracted strong attention from both researchers and industry engineers and was selected as one of the event’s top papers.

One of the main technical challenges was preventing electrical interference between the stacked layers. When transistors are placed so closely together, signals from the upper layer can disrupt the lower one, potentially causing malfunction. Samsung Electronics said it overcame this issue by introducing a specialized insulating layer between the tiers. Each layer also incorporates three nanosheet channels, allowing electrical current to flow more efficiently.

The company also set a new density benchmark by reducing the gate pitch—a key measurement of transistor size—to 42 nanometers from 48 nanometers, which it claims is the smallest achieved for this type of architecture. A smaller gate pitch means more transistors can be fitted into the same physical space, boosting overall performance.

Industry experts say this development reflects a broader shift in semiconductor design: instead of only shrinking transistors on a flat surface, engineers are now exploring vertical stacking as the next frontier. This evolution mirrors earlier advances in memory technologies such as high-bandwidth memory and NAND flash, suggesting that logic chips like CPUs may be entering a three-dimensional era.

The potential applications are particularly important for artificial intelligence and high-performance computing, where demand for processing power continues to rise rapidly while energy efficiency remains critical.

“This will be the most suitable structure for logic chips in the AI era, which need to process more computation in a smaller area at lower power,” said Hwang Dong-hoon, a principal engineer at Samsung Electronics’ Semiconductor Research and Development Center.

Analysts also note that if this approach proves scalable in mass production, it could significantly reshape the global semiconductor competition, especially as companies race to support next-generation AI models that require ever-increasing computational density.